In order for a typical digital processing system to function, a synchronous mechanism such as clock(s) and/or oscillator(s) is used to coordinate data processing by various digital devices and/or components such as read and write operations. Modern digital devices, such as processors, routers, wireless computing systems, or communication controllers, typically include one or more clocks to synchronize and facilitate data processing. A clock, which is also known as oscillator or crystal, oscillates or vibrates at a specific frequency, normally measured in megahertz (millions of cycles per second) (“MHz”).
A clock “tick,” also known as a clock cycle, is typically considered as the smallest unit of time in which data processing such as a read operation takes place. The clock cycle is what, for example, drives various components or circuits within a digital system to perform some functional tasks. The faster the clock ticks, the more performance can typically be rendered by a computing machine or system.
A problem associated with a digital processing device or system is that a system will go down when its system clock fails. When a system clock stops ticking, a processor or central processing unit (“CPU”) within a computing system fails or crashes as soon as the clock ceases to oscillate (or tick). When the processor stops working, the system shuts down. If the system is down due to clock failure, the diagnostic unit will not be able to interrogate reasons of failure because the diagnosis unit requires a functioning clock to perform various diagnostic tasks. As such, a digital processing system typically requires a major repair such as replacing motherboard when its clock system stops working.
A conventional approach to mitigate impact of clock failure is to employ a sophisticated Application-Specific Integrated Circuit (“ASIC”) clock recovery component for clock backup. A drawback associated with the conventional approach is its complicated design and high cost for the additional ASIC component.
An alternative approach to resolve system clock failure is to use a clock signal distribution scheme with a master clock feeding to multiple slave clocks. The drawback associated with this approach is that when the master clock fails, the slave clocks stop working as well.